Tolerance of delay faults

Author

Walker, D.M.H.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1992

fDate

4-6 Nov 1992

Firstpage

207

Lastpage

216

Abstract

Defect tolerance is traditionally concerned with maintaining system function in the face of spot defects that cause catastrophic circuit faults, such as shorts and opens. This paper describes the problem of spot defects that cause delay faults, and how they can be modeled and characterized in an IC fabrication line. A procedure for simulating the occurrence of such delay faults in a design is described, and results for a number of examples are given. Some techniques for tolerance of delay faults at the architectural and algorithmic level are described

Keywords

VLSI; delays; fault location; integrated circuit manufacture; semiconductor process modelling; IC fabrication line; algorithmic level; catastrophic circuit faults; defect tolerance; delay faults; opens; shorts; spot defects; system function; CMOS technology; Circuit faults; Circuit simulation; Delay estimation; Fabrication; Integrated circuit modeling; Maintenance engineering; Manufacturing processes; Propagation delay; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224354

Filename

224354

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3210744