Defect level estimation for digital ICs

Author

Sousa, J.J.T. ; Teixeira, J.P.

Author_Institution

INESC, IST, CEAUTL, Lisboa, Portugal

fYear

1992

fDate

4-6 Nov 1992

Firstpage

32

Lastpage

41

Abstract

Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to physical defects. A definition of weighted fault coverage is introduced, and an extension of Williams formula to handle non-equiprobable faults is proposed. Results of applying this method to a set of real IC design examples confirm the usefulness of this approach

Keywords

VLSI; digital integrated circuits; fault location; DL estimation; IC design; Williams formula; defect levels; digital ICs; fault model; market competitiveness; non-equiprobable faults; weighted fault coverage; Circuit faults; Circuit testing; Digital integrated circuits; Integrated circuit modeling; Integrated circuit testing; Predictive models; Production; Semiconductor device measurement; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224363

Filename

224363