• DocumentCode
    3210895
  • Title

    Comparing results from defect-tolerant yield models

  • Author

    Thibeault, C. ; Savaria, Y.

  • Author_Institution
    Dept. of Math. & Comput. Sci., Quebec Univ., Montreal, Que., Canada
  • fYear
    1992
  • fDate
    4-6 Nov 1992
  • Firstpage
    22
  • Lastpage
    31
  • Abstract
    To date, many models have been developed to predict the yield of defect-tolerant integrated circuits (ICs). In this paper, results obtained from several of these models are compared. Their sensitivity to various model parameters is also examined. These results lead one to conclude that, despite differences in the predicted amount of redundancy, it may be possible to obtain good solutions. The differences in the solutions come from the models as well as from the parameters used in these models, and solutions are said to be good when the resulting figures of merit are rather insensitive. Consequently, a simple method is proposed to select the number of spares to add in defect-tolerant ICs
  • Keywords
    VLSI; monolithic integrated circuits; redundancy; semiconductor process modelling; defect-tolerant integrated circuits; defect-tolerant yield models; model parameters; redundancy; sensitivity; spares; Computer science; Equations; Integrated circuit modeling; Integrated circuit yield; Mathematical model; Mathematics; Predictive models; Redundancy; Semiconductor device modeling; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
  • Conference_Location
    Dallas, TX
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-2837-5
  • Type

    conf

  • DOI
    10.1109/DFTVS.1992.224366
  • Filename
    224366