On the design and optimization of a switched-capacitor interface circuit for MEMS capacitive sensors

In this paper a switched-capacitor (SC) interface circuit that is intended for MEMS capacitive sensors is proposed and designed. In the proposed architecture, both correlated double sampling (CDS) and chopper stabilization (CHS) noise reduction techniques are applied to the interface circuit to reduce the amplifier offset and low frequency noise. The effects of parasitic capacitances between the sensor and its interface circuit which are usually larger than the sense capacitances are carefully analyzed and used to optimize the readout performance. In other words, by analyzing the circuit offset and noise performance in presence of these parasitic capacitances, the suitable values of the circuit parameters such as sampling frequency, chopping frequency, and amplifier unity gain bandwidth are calculated. In comparison to the circuit using only CDS or CHS technique, the resolution variation of the proposed readout circuit is less than 1aF in presence of parasitic capacitances varying up to 20 pF.