A real-time reconfiguration algorithm for fault-tolerant VLSI and WSI arrays

Author

Al-Asaad, Hussain ; Vai, Mankuan

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., MA, USA

fYear

1992

fDate

4-6 Nov 1992

Firstpage

52

Lastpage

59

Abstract

Reliability is an important issue in the real-time operations of VLSI array processors. A new algorithm for the real-time reconfiguration of VLSI and WSI arrays is presented. This algorithm is characterized by its simplicity and locality. The control of this reconfiguration scheme is implemented in hardware for a real time execution. It supports multiple faults including transient/intermittent faults with a zero degradation time. Simulation results show that a good spare utilization rate is achieved with a computational complexity that is independent of the array size

Keywords

VLSI; fault tolerant computing; parallel architectures; VLSI; WSI; array processors; computational complexity; locality; multiple faults; real-time operations; real-time reconfiguration algorithm; transient/intermittent faults; utilization rate; zero degradation time; Adaptive arrays; Automatic testing; Built-in self-test; Clustering algorithms; Degradation; Fault tolerance; Hardware; Logic arrays; Redundancy; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224368

Filename

224368