The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology

This paper will demonstrate the effect of deep trench (DT) on the latchup robustness of an 0.13 μm 200 GHz BiCMOS SiGeC HBT technology. Guard ring efficiency is evaluated using deep trench guard ring structures and compared to standard p+ and n-well guard ring structures. The latchup robustness is evaluated using pnpn structures with a deep trench perimeter on the edge of the well structure. Latchup robustness of pnpn structures is evaluated as a function of trench depth where the deep trench serves as a guard ring for the n-well region. Key latchup metrics, such as turn-on, trigger and sustaining voltage and current conditions, for a range of p+/n+ spacings as a function of trench depth, and external well and external substrate resistance is quantified. Trigger contours in a linear-logarithm space of trench depth and substrate resistance form a design space for optimization of latchup. Experimental results show that utilizing deep trench structure, and substrate contact spacing allows for latchup robustness in a low doped p-substrate wafer technology.