A new experimental method for evaluating electric field at the junctions of DRAM cell transistors and the effect of electric field strength on the retention characteristics of DRAM

A new method for the analysis of DRAM data retention characteristics is developed. We use a test element group (TEG) and detailed simulation to analyze the bias dependence of the junction leakage currents of DRAM. We consequently develop an experimental method for the evaluation of electric field at the junctions of DRAM cell transistors. In this analysis, not only are storage-node and Substrate bias considered; word-line bias is also taken into account. The method is used to confirm, for the first time the relationship between the electric field and the tail component of the retention-time distribution through experiment rather than simulation. The method provides a useful way to evaluate the retention characteristics for manufactured DRAM in terms of electric field. Since it is applicable to all generation of DRAM, the method will be a powerful tool for the design of DRAMs with adequate retention time.