DocumentCode
3211086
Title
Arithmetic codes for concurrent error detection in artificial neural networks: the case of AN+B codes
Author
Piuri, Vincenzo ; Sami, Mariagiovanna ; Stefanelli, Renato
Author_Institution
Dept. of Electron., Politecnico di Milano, Italy
fYear
1992
fDate
4-6 Nov 1992
Firstpage
127
Lastpage
136
Abstract
A number of digital implementations of neural networks have been presented in recent literature. Moreover, several authors have dealt with the problem of fault tolerance; whether such aim is achieved by techniques typical of the neural computation (e.g. by repeated learning) or by architecture-specific solutions, the first basic step consists clearly in diagnosing the faulty elements. The present paper suggests adoption of concurrent error detection; the granularity chosen to identify faults is that of the neuron. An approach based on a class of arithmetic codes is suggested; various different solutions are discussed, and their relative performances and costs are evaluated. To check the validity of the approach, its application is examined with reference to multi-layered feed-forward networks
Keywords
error detection codes; fault tolerant computing; feedforward neural nets; architecture-specific solutions; arithmetic codes; artificial neural networks; concurrent error detection; fault tolerance; faulty elements; granularity; multi-layered feed-forward networks; neural computation; Arithmetic; Artificial neural networks; Circuit faults; Computer aided software engineering; Costs; Fault diagnosis; Feedforward systems; Intelligent networks; Neurons; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location
Dallas, TX
ISSN
1550-5774
Print_ISBN
0-8186-2837-5
Type
conf
DOI
10.1109/DFTVS.1992.224376
Filename
224376
Link To Document