Title :
Design for testability in a 200 MFLOPS vector-pipelined processor (VPP)-ULSI
Author :
Hagihara, Yasuhiko ; Ohkubo, Chie ; Okamoto, Fuyuki ; Yamada, Hachiro ; Takada, Masahide ; Enomoto, Tadayoshi
Author_Institution :
NEC Corp., Tokyo, Japan
Abstract :
The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-pipelined processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for pipelined arithmetic units, achieved by a BIST with ~1,000,000(220) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU
Keywords :
VLSI; automatic test equipment; boundary scan testing; built-in self test; design for testability; digital arithmetic; fault location; microprocessor chips; parallel machines; pipeline processing; random processes; vector processor systems; 200 MFLOPS; 64 bits; BIST; ULSI; built-in self tests; design for testability; fault coverage; floating point processor; internal partial scan; random pattern; register file; scan test; vector-pipelined processor; Arithmetic; Built-in self-test; Centralized control; Design for testability; Laboratories; Logic testing; Radio frequency; Registers; Sequential analysis; Ultra large scale integration;
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
DOI :
10.1109/ATS.1992.224404
