Process impact on SRAM alpha-particle SEU performance

A single poly, 0.15 μm process has been modified to fabricate a 18 Mb fast synchronous memory for evaluation of the process impact on the a-particle SEU (single Event Upset) performance. The process options include (1)increasing the source/drain junction capacitance, (2)adding a backend capacitor between the storage nodes, and (3)using the epitaxial substrate. In addition, the fraction factorial splits were carried out for other implants, such as n-well and p-well processes to quantify their impact on the SEU FIT rate. The P-Latch transistor drive current and threshold voltages have been changed as well to explore the influence on the SRAM α-ASER. It is found that the most effective method to improve the SEU FIT rate is to add additional capacitor, followed by the junction capacitance increase. The rest of the process options have only a secondary impact on the SRAM ASER.