Synthesis for testability of PLA based finite state machines

A new procedure for the synthesis of easily testable PLA-based finite state machines is presented. All combinational irredundant crosspoint faults in the PLA implementing the combinational component of the machine are testable. The machines produced have short machine-independent justification sequences for each state. The maximum length of these sequences is nv. A unit length sequence verifies that the machine has been actually placed in the reset state after the application of the reset input. The authors have developed an algorithm which does not use fault simulation. Combinational fault simulation is introduced in order to reduce the number of test vectors needed. There is an area overhead associated to the increment in testability. These area penalties have been shown to be smaller for larger machines. The scheme reduces the area overhead of similar approaches previously reported