Title :
Break fault model and fault collapsing analysis for PLA´s
Author :
Hwang, Gwo-Haur ; Shen, Wen-Zen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Abstract :
The behavior of break faults in PLAs is analyzed and a fault collapsing technique for the faults is presented. From the behavioral analysis, two patterns are needed to detect a break fault. By the fault collapsing technique, the number of break faults is reduced from 2×(#device)+(#output) to less than 2×(#input+#product)+(#output). Experimental results show that, for 56 benchmarks, the number of break faults after fault collapsing is reduced to 18.37%
Keywords :
VLSI; fault location; integrated circuit testing; logic arrays; logic testing; performance evaluation; behavioral analysis; benchmarks; break fault; fault collapsing analysis; Circuit faults; Circuit synthesis; Combinational circuits; Fault detection; Pattern analysis; Programmable logic arrays; Sequential circuits; Test pattern generators; Testing; Very large scale integration;
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
DOI :
10.1109/ATS.1992.224412
