A novel all NMOS leakage feedback with data retention technique

Author

Lorenzo, Rohit ; Chaudhary, Shubham

Author_Institution

Electr. Eng., NIT Silchar, Silchar, India

fYear

2013

fDate

16-18 Dec. 2013

Firstpage

1

Lastpage

5

Abstract

In this paper we propose a new structure for NMOS based leakage feedback approach. The new proposed circuit technique includes NMOS only sleep transistors in parallel to both pull-up and pull-down paths which will reduce subthreshold current while saving the exact logic state. Based on 45nm Berkeley predictive technology model (BSIM 4), post layout simulation on microwind shows that as compared to conventional logic, the proposed design with a supply voltage of 0.9 V at 27°C achieves better power and delay performance than conventional design.

Keywords

MOSFET; semiconductor device models; BSIM 4; Berkeley predictive technology model; NMOS-based leakage feedback approach; NMOS-only sleep transistors; circuit technique; conventional logic; data retention technique; logic state; microwind; post layout simulation; pull-up pull-down paths; size 45 nm; subthreshold current reduction; temperature 27 degC; voltage 0.9 V; Delays; Integrated circuit modeling; MOSFET; Subthreshold current; Switching circuits; leakage power dissipation; power gating; sleep transistor and transistor stacking; sub threshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Automation, Robotics and Embedded Systems (CARE), 2013 International Conference on

Conference_Location

Jabalpur

Type

conf

DOI

10.1109/CARE.2013.6733701

Filename

6733701