VLSI layout of a pipelined multiplier

The proposed multiplier views the operations as a logical one, without using addition or counting. Such a novel view provides grounds for a high pipeline throughput. The authors discuss the algorithm and then the cell design, cell placement, and a routing scheme in the VLSI layout of the proposed multiplier using CMOS technology. Then they compare their design against a number of recently proposed systolic multipliers, using multiplication delay as the comparison measure. They conclude that the proposed design outperforms most of the existing schemes for different multiplication sizes.<>