Finding voids in dual damascene Cu vias and their impact on reliability

Copper has a lower electrical resistance and a higher electromigration resistance than Al/Cu, meaning that higher current densities or low powers can he allowed for an increased packing density. With specific processes, Dual damascene and ECP (Electrical chemical plating), Cu interconnection has a lower total cost, a better performance, and improved reliability. In 0.13 μm technologies, Cu is the best choice to replace the conventional Al/Cu interconnection. Defect identification and reduction are among the most important tasks during development of high performance Cu interconnections. Defect reduction ultimately improves yield and reliability, reduces fabrication cost, and increases the profit for IC manufacturers. This paper presents the identification of a major problem, voids in vias, in advanced 0.13 μm Cu interconnection process development. The problem was identified on single via test patterns, via chain test patterns, and SRAM test qualification vehicles. We used a variety of failure analysis tools and techniques to provide timely results on selected low yield wafers. The failure localization methods include passive voltage contrast, OBIRCH (Optical Beam Induced Resistance Change) and SRAM functional tests. The physical analysis methods include FIB (Focus Ion Beam) and TEM (Transmission Electronic Microscopy). We have identified several kinds of voids in Cu vias, which will be discussed in detail. Particularly, we will introduce the impact on reliability resulting from via voids.