A concurrent fault detection method for superscalar processors

Author

Pawlovsky, Alberto Palacios ; Hanawa, Makoto

Author_Institution

Hitachi Central Res. Lab., Hitachi Ltd., Koigakubo, Japan

fYear

1992

fDate

26-27 Nov 1992

Firstpage

139

Lastpage

144

Abstract

The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction´s slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processor´s pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction

Keywords

computer testing; fault location; parallel architectures; pipeline processing; reduced instruction set computing; ILP processor; branch addresses; computer testing; concurrent fault detection; execution; instruction level parallel processor; no operation instruction; pipelines; superscalar RISC processor; Automatic testing; Circuit testing; Computer aided instruction; Delay; Fault detection; Hardware; Parallel processing; Pipeline processing; Reduced instruction set computing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)

Conference_Location

Hiroshima

Print_ISBN

0-8186-2985-1

Type

conf

DOI

10.1109/ATS.1992.224418

Filename

224418