Optical test pixels implemented in a standard CMOS technology

The performances of optical pixels are not well modeled in standard tools used by ASIC designers. Hence, empirical knowledge based on a library of implemented and measured pixels is necessary. Such basis is especially important when designing for high sensitivity for weak signals. An optimal design should collect sufficient charge; have a good charge to voltage conversion ratio and low noise and leakage current. As a partner in a European project SINTEF implemented a front end circuit containing 520 times 40 pixels, amplifiers and ADCs. As an additional add-on some test pixels where included to get more empirical expertise on the performance of different pixel architectures. This paper will report on the test pixels only and ignore the main purpose and application of the chip.