Title :
Test set compaction for combinational circuits
Author :
Chang, Jau-Shien ; Lin, Chen-Shang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Test set compaction for combinational circuits is studied. Two active compaction methods, forced pair-merging and essential fault pruning, are developed to reduce a given test set. Together these two methods, the compacted test size is smaller than known best results by more than 20% and is only 20% larger than the established lower bound
Keywords :
combinatorial circuits; fault location; logic testing; active compaction; combinational circuits; essential fault pruning; forced pair-merging; logic testing; test set compaction; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Logic testing; Performance evaluation; Robustness; Test pattern generators;
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
DOI :
10.1109/ATS.1992.224429
