Title :
Area efficient pseudo-parallel Galois field multipliers
Author :
Mathew, J. ; Rahaman, H. ; Jabir, A.M. ; Pradhan, D.K.
Author_Institution :
Univ. of Bristol, Bristol
Abstract :
This paper presents a new method for implementing Galois field multipliers over polynomial basis. The proposed method minimizes the number logic gates by reusing the same hardware. The proposed architecture can be adaptively resized according to the requirement, thereby giving more design flexibility. Design analysis based 0.18 micron technology shows that the proposed design with minimum latency is area/power efficient for finite field multipliers of size greater than 10.
Keywords :
Galois fields; logic design; logic gates; multiplying circuits; design analysis; finite field multiplier; number logic gates; polynomial basis; pseudoparallel Galois field multiplier; size 0.18 micron; Computer architecture; Cryptography; Delay; Galois fields; Hardware; Logic gates; Modules (abstract algebra); Polynomials; Signal design; Signal generators;
Conference_Titel :
Norchip, 2007
Conference_Location :
Aalborg
Print_ISBN :
978-1-4244-1516-8
Electronic_ISBN :
978-1-4244-1517-5
DOI :
10.1109/NORCHP.2007.4481033
