Area efficient pseudo-parallel Galois field multipliers

This paper presents a new method for implementing Galois field multipliers over polynomial basis. The proposed method minimizes the number logic gates by reusing the same hardware. The proposed architecture can be adaptively resized according to the requirement, thereby giving more design flexibility. Design analysis based 0.18 micron technology shows that the proposed design with minimum latency is area/power efficient for finite field multipliers of size greater than 10.