DocumentCode
3211825
Title
Reduction of dynamic memory usage in concurrent fault simulation for synchronous sequential circuits
Author
Kim, Kyuchull ; Saluja, Kewal K.
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
1992
fDate
26-27 Nov 1992
Firstpage
40
Lastpage
45
Abstract
A strategy that reduces the memory usage to minimum is proposed and implemented. The results of implementation show that the dynamic memory usage of the concurrent fault simulator considered is indeed lower than other commonly used memory management strategies. It is shown through experimentation that the reduced memory usage improves substantially the performance of the concurrent fault simulator
Keywords
digital simulation; fault location; logic testing; sequential circuits; storage management; concurrent fault simulation; dynamic memory usage; synchronous sequential circuits; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Concurrent computing; Current measurement; Fault diagnosis; Iterative methods; Memory management; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location
Hiroshima
Print_ISBN
0-8186-2985-1
Type
conf
DOI
10.1109/ATS.1992.224433
Filename
224433
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