DocumentCode
3211857
Title
Self-Adjusting Output Data Compression for RAM with Word Error Detection and Correction
Author
Musin, S.B. ; Ivaniuk, A.A. ; Yarmolik, V.N.
Author_Institution
Belarusian State Univ. of Inf. & Radioelectron., Minsk
fYear
2007
fDate
21-23 June 2007
Firstpage
535
Lastpage
538
Abstract
This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.
Keywords
built-in self test; data compression; embedded systems; error correction; error detection; integrated circuit reliability; integrated circuit testing; integrated memory circuits; random-access storage; system-on-chip; RAM; built-in self-test architecture; double word error detection; self-adjusting output data compression; single word error correction; single word error detection; Built-in self-test; Circuit testing; Data compression; Error correction; Error correction codes; Informatics; Performance evaluation; Polynomials; Random access memory; Read-write memory; BIST; RAM; Word error;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location
Ciechocinek
Print_ISBN
83-922632-9-4
Electronic_ISBN
83-922632-9-4
Type
conf
DOI
10.1109/MIXDES.2007.4286220
Filename
4286220
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