A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits

Author

Mason, P.W. ; La Duca, A.J. ; Holder, C.H. ; Alam, M.A. ; Hwang, D.K.

Author_Institution

Agere Syst., Allentown, PA, USA

fYear

2004

fDate

25-29 April 2004

Firstpage

430

Lastpage

434

Abstract

We present a comprehensive methodology for modeling, as a function of time, increased standby leakage current of VLSI circuits due to soft-breakdown. Predictions, using a post-soft-breakdown leakage-scaling model and device-level time-dependent dielectric breakdown (TDDB) data, agree remarkably well with observations of circuit leakage. The implications of this predictive model for the leakage current regarding the appropriate evaluation of the absolute reliability of intrinsic, ultra-thin oxides are discussed.

Keywords

VLSI; electric breakdown; integrated circuit modelling; integrated circuit reliability; leakage currents; VLSI circuits; absolute reliability; accurate assessment; device-level time-dependent dielectric breakdown; post-soft-breakdown leakage-scaling model; reliability; soft-broken gate oxide leakage; standby leakage current; ultra-thin oxides; Circuit testing; Electric breakdown; Integrated circuit reliability; Integrated circuit testing; Inverters; Leakage current; Predictive models; Reliability theory; Stress; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International

Print_ISBN

0-7803-8315-X

Type

conf

DOI

10.1109/RELPHY.2004.1315366

Filename

1315366