The MPC505 RISC microcontroller

Author

Melear, Charles

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1994

fDate

11-13 Oct 1994

Firstpage

119

Lastpage

123

Abstract

The MPC505 microcontroller is the first implementation of a new family of microcontrollers that features a reduced instruction set (RISC) architecture based on the PowerPC architecture. The internal architecture of the MPC505 implements a 32-bit structure. This architecture provides 32-bit effective addresses, integer data types of 8-, 16-, and 32-bits and floating point data types of 32 and 64 bits. A simplified block diagram of the MPC505 is shown. The MPC505 is designed to operate at 3.3 volts. Along with power conservation features, such as clock speed reduction, the MPC505 can operate on a relatively modest power budget

Keywords

reduced instruction set computing; 3.3 V; 32 bit; MPC505 RISC microcontroller; PowerPC architecture; clock speed reduction; effective addresses; floating point data; integer data types; power conservation features; reduced instruction set; Clocks; Influenza; Microcontrollers; Reduced instruction set computing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Northcon/94 Conference Record

Conference_Location

Seattle, WA

Print_ISBN

0-7803-9995-1

Type

conf

DOI

10.1109/NORTHC.1994.643321

Filename

643321

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3211967