A VLSI data compression chip for high-speed image compression

Author

Chang, Yi-Chieh ; Kapoor, Pankaj ; Joshi, Rakesh ; Suriano, Miguel

Author_Institution

Dept. of Electr. Eng., Texas Univ., El Paso, TX, USA

fYear

1994

fDate

11-13 Oct 1994

Firstpage

126

Lastpage

130

Abstract

A VLSI chip has been designed to perform a high-speed pyramid data compression algorithm for image processing. The algorithm implemented in the VLSI chip requires dramatically less computations yet it is an effective technique to perform the data compression. The computational complexity of the algorithm is at least 10 times less than that of the standard algorithm, JPEG while offering comparable performances in image quality to JPEG. Moreover, due to the simplified computational algorithm, the hardware complexity will be 3 to 4 times less than the VLSI chips based on JPEG, thus the cost/performance of the proposed VLSI data compression chip will be 30 to 40 times cheaper than any existing standard data compression chip

Keywords

VLSI; VLSI; computational complexity; data compression chip; high-speed image compression; image quality; pyramid data compression algorithm; Algorithm design and analysis; Computational complexity; Costs; Data compression; Hardware; Image coding; Image processing; Image quality; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Northcon/94 Conference Record

Conference_Location

Seattle, WA

Print_ISBN

0-7803-9995-1

Type

conf

DOI

10.1109/NORTHC.1994.643323

Filename

643323