DocumentCode :
3212020
Title :
On generating high quality tests for transition faults
Author :
Shao, Yun ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
2002
fDate :
18-20 Nov. 2002
Firstpage :
1
Lastpage :
8
Abstract :
In this work we propose a path-oriented test generation procedure called POTENT to generate high quality tests for transition faults. Both weak non-robust and strong non-robust tests can be generated by POTENT. We classify, transition fault tests into six types according to their activation and propagation methods. The basic idea of POTENT is to test a transition fault along a longest testable path passing through the fault site. For transition faults that are activated or propagated through multipaths, heuristics are proposed to maximize the propagation delay of the target fault. We also propose an efficient method to evaluate the quality of a given transition fault test set. Experimental results show that POTENT generates higher quality transition fault test sets than the conventional test generation method.
Keywords :
automatic test pattern generation; delays; fault diagnosis; integrated circuit testing; logic testing; ATPG; POTENT; activation methods; fault models; gate delay faults; heuristics; high quality tests; path-oriented test generation; propagation delay; propagation methods; strong nonrobust tests; transition fault test set; transition faults; weak nonrobust tests; Circuit faults; Circuit testing; Cities and towns; Clocks; Delay effects; Fault detection; Logic circuits; Logic testing; Propagation delay; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1825-7
Type :
conf
DOI :
10.1109/ATS.2002.1181676
Filename :
1181676
Link To Document :
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