Title :
Path delay fault simulation algorithms for sequential circuits
Author :
Chakraborty, Tapan J. ; Agrawal, Vishwani D. ; Bushnell, Michael L.
Author_Institution :
AT&T Bell Labs., Princeton, NJ, USA
Abstract :
The authors present a differential algorithm for concurrent simulation of path delay faults in sequential circuits. The simulator determines all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output, by analyzing vector-pairs and the hazard states occurring between vectors
Keywords :
digital simulation; fault location; logic testing; sequential circuits; concurrent simulation; differential algorithm; fault effect; fault simulation algorithms; hazard states; initialization; logic testing; path delay faults; sequential circuits; signal transition propagation; vector-pairs; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Delay effects; Logic arrays; Logic testing; Propagation delay; Sequential circuits;
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
DOI :
10.1109/ATS.1992.224444
