An FPGA Implementation of the Distributed Arithmetic Based Quaternionic Multipliers for Paraunitary Filter Banks

Author

Verenik, A. ; Parfieniuk, M. ; Petrovsky, A.

Author_Institution

Belarusian State Univ. of Inf. & Radioelectron., Minsk

fYear

2007

fDate

21-23 June 2007

Firstpage

605

Lastpage

610

Abstract

If a digital paraunitary filter bank (PUFB) designed using hypercomplex number theory is to be implemented in hardware, the throughput and chip area of used quaternion multipliers are of critical importance. In this paper, digit (L-bit)-serial quaternion multipliers based on the distributed arithmetic are presented as circuits well suited for FPGA-based fixed-point implementations of PUFBs. Apart from a theoretical development, experimental design results obtained using a Xilinx Virtex FPGA are reported.

Keywords

channel bank filters; distributed arithmetic; field programmable gate arrays; number theory; FPGA-based fixed-point implementations; Xilinx Virtex FPGA; digit-serial quaternion multipliers; distributed arithmetic based quaternionic multipliers; hypercomplex number theory; paraunitary filter banks; Channel bank filters; Digital arithmetic; Field programmable gate arrays; Filter bank; Fixed-point arithmetic; Hardware; Informatics; Quantization; Quaternions; Throughput; FPGA; Hypercomplex number; Paraunitary filter bank; Quaternion; distributed arithmetic; multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

Conference_Location

Ciechocinek

Print_ISBN

83-922632-9-4

Electronic_ISBN

83-922632-9-4

Type

conf

DOI

10.1109/MIXDES.2007.4286234

Filename

4286234