Title :
A state reduction method for non-scan based FSM testing with don´t care inputs identification technique
Author :
Hosokawa, Toshinori ; Date, Hiroshi ; Muraoka, Michiaki
Author_Institution :
Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan
Abstract :
This paper proposes a state reduction method for non-scan based FSM (finite state machine) testing with a don´t care inputs identification technique. States for FSM testing are classified into valid test states and invalid test states. This method reduces the numbers of invalid test states and valid test states using a don´t care input identification technique and a state compaction technique. The test length may be shortened by reducing the number of valid test states and additional test area is reduced by reducing the number of invalid test states. Experimental results for MCNC´91 FSM benchmarks and practical FSMs show that the proposed method reduces the test area by 13 to 77% and shortens the test lengths by 10 to 36%.
Keywords :
circuit simulation; design for testability; finite state machines; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; performance evaluation; DFT; FSM nonscan based testing; FSM test state classification; benchmark testing; design for testability; don´t care inputs identification techniques; finite state machines; invalid test states; state compaction techniques; state reduction methods; test area reduction; test length reduction; valid test states; Ambient intelligence; Testing;
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
Print_ISBN :
0-7695-1825-7
DOI :
10.1109/ATS.2002.1181685