DocumentCode
3212254
Title
A logic synthesis system based on global dynamic extraction and flexible cost
Author
Chen, Yulin ; Tsai, Wei Kang ; Kurdahi, Fadi J.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
fYear
1993
fDate
5-6 Mar 1993
Firstpage
123
Lastpage
126
Abstract
An efficient algorithm for a logic synthesis system based on global dynamic extraction and flexible cost (GDEF) is described. The GDEF is designed to find the best common subexpression and to update the value of the other common subexpressions dynamically. The GDEF feedbacks approximate layout area obtained through an area-estimation program to guide the logic synthesis process. In this approach, the cost function is dependent on both literal count and estimated area
Keywords
circuit layout CAD; logic CAD; CAD; approximate layout area; area-estimation program; flexible cost; global dynamic extraction; logic synthesis system; Area measurement; Circuits; Cost function; Feedback; Kernel; Logic design; Routing; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224465
Filename
224465
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