DocumentCode
3212276
Title
Adaptive bounded time windows in an optimistically synchronized simulator
Author
Palaniswamy, Avinash C. ; Wilsey, Philip A.
Author_Institution
Center for Digital Syst. Eng., Cincinnati Univ., OH, USA
fYear
1993
fDate
5-6 Mar 1993
Firstpage
114
Lastpage
118
Abstract
The authors address one problem of speeding parallel digital system simulation using time warp, namely, that logical processes with errant behavior can incur considerable rollback behavior (analogous to thrashing in paging virtual memories). Consequently, additional mechanisms must be added to an optimistically synchronized simulator to inhibit excessive rollback. They describe a method of adaptively sizing bounded time windows to balance lookahead processing
Keywords
VLSI; circuit analysis computing; digital simulation; parallel processing; synchronisation; VHDL; adaptive bounded time windows; lookahead processing; optimistically synchronized simulator; parallel digital system simulation; rollback behavior; time warp; Circuit simulation; Contracts; Digital systems; Integral equations; Modeling; Monitoring; Parallel machines; Systems engineering and theory; Time warp simulation; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224467
Filename
224467
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