Abstract :
An automated, structured process was developed to strategically focus the package selection of VLSI systems. A structured computer-aided engineering program was developed to anticipate, rather than simply react to, the life-cycle implications of the packaging selection. This tool provides the user with quick what-if analysis on various packaging implementations of the targeted electronic system during the conceptual phase. Input to the estimator is a description of the number and types of components of the system. Output is a component count comparison of six different technology implementations of the same system. The technologies currently implemented are discrete/IC, field programmable gate array, application-specific integrated circuit, hybrid microelectronic assembly, multichip module, and monolithic wafer-scale integration. In addition, the output includes tradeoffs due to gate counts, engineering costs, production costs, circuit board areas, power, and reliability
Keywords :
VLSI; electronic engineering computing; integrated circuit technology; packaging; ASIC; FPGA; MCM; VLSI systems; WSI; application-specific integrated circuit; computer-aided engineering; estimator; field programmable gate array; hybrid microelectronic assembly; monolithic wafer-scale integration; multichip module; packaging selection; structured CAE program; Application specific integrated circuits; Assembly; Costs; Electronics packaging; Field programmable gate arrays; Hybrid integrated circuits; Integrated circuit technology; Microelectronics; Monolithic integrated circuits; Very large scale integration;
Conference_Titel :
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
