An IEEE 754 floating point engine designed with an electronic system level methodlogy

This paper presents the design and implementation of an IEEE 754-compliant, single-precision, coarse-level pipelined floating point engine designed using a new Electronic System Level tool. The starting point was the Softfloat ANSI-C implementation of the standard. Minimal modifications, in the form of two parallel processes, were introduced to map the ANSI-C code to the Input/Output interface of a cardbus-based field-programmable gate array prototyping board. The remaining part of the code was directly synthesized to gates using Cebatech´s C2R compiler and a number of configurations were studied with various degrees of functional-unit sharing and capabilities. Preliminary results clearly identify the potential of next generation ESL tools in transforming control-oriented applications written in ANSI-C code directly to synthesizable verilog, in record time. At the same time, the generated silicon exhibits up to two orders of magnitude better cycle performance compared to the Softfloat standard executing on an in-order superscalar processor (simulated) thus making a strong statement for the suitability of the ESL tool for the silicon synthesis of control-dominated applications. The design was validated both at the C-level as well as on an E14 PicoComputing FPGA board were it achieved an operating frequency of 64 MHz.