A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits

Author

Pomeranz, Irith ; Reddy, Sudhakar M.

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2002

fDate

18-20 Nov. 2002

Firstpage

110

Lastpage

115

Abstract

We describe a built-in test pattern generation method for delay faults in scan circuits based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the stored sets. The sizes of the sets are minimized before they are stored on-chip in order to reduce the storage requirements and the test application time. The delay fault model we consider is the transition fault model.

Keywords

automatic test pattern generation; boundary scan testing; built-in self test; delays; integrated circuit design; integrated circuit testing; logic design; logic partitioning; logic testing; TPG; delay transition fault models; on-chip test set size minimization; partitioning based built-in test pattern generation; precomputed test set; primary input values; scan circuit delay faults; state variables; storage based built-in test pattern generation; storage requirements; stored sets Cartesian product; test application time; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Delay; Electrical fault detection; Fault detection; Flip-flops; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1825-7

Type

conf

DOI

10.1109/ATS.2002.1181696

Filename

1181696