Super Stack technique to reduce leakage power for sub 0.5-V supply voltage in VLSI circuits

Leakage current of CMOS circuits has become a major factor in very deep submicron regime. ITRS reports that leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small. In this paper a leakage reduction technique named "Super stack"for sub 0.5-V supply voltage has been proposed. Super Stack technique comes in handy where Multithreshold techniques fail to apply for 0.5-V or lower supply voltages. The proposed method can be used in sub 0.5 V supply voltage for reducing the leakage power in active mode and standby mode while reducing the delay.