Title :
A scheduling method in high-level synthesis for acyclic partial scan design
Author :
Inoue, Tomoo ; Miura, Tomokazu ; Tamura, Akio ; Fujiwara, Hideo
Author_Institution :
Fac. of Inf. Sci., Hiroshima City Univ., Japan
Abstract :
Acyclic partial scan design is an efficient DFT method. This paper presents a scheduling method for reducing the number of scan registers for an acyclic structure. In order to estimate the number of scan registers during scheduling, we propose provisional binding of operational units, and show a force-directed scheduling algorithm with the provisional binding. Experimental results show that the number of scan registers in the resulting RTL datapaths can be reduced by our method combined with the binding algorithm for acyclic partial scan.
Keywords :
boundary scan testing; circuit CAD; design for testability; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; scheduling; DFT methods; RTL datapaths; acyclic partial scan binding algorithm; acyclic partial scan design; design-for-testability; high-level synthesis scheduling methods; operational unit provisional binding; register-transfer level; scan register number reduction; Algorithm design and analysis; Circuit testing; Design for testability; Flow graphs; High level synthesis; Job shop scheduling; Logic design; Scheduling algorithm; Sequential analysis; Sequential circuits;
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
Print_ISBN :
0-7695-1825-7
DOI :
10.1109/ATS.2002.1181699