Leakage power reduction in CMOS modulo4 adder and modulo4 multiplier in sub-micron technology

Leakage is the only source of power consumption in an idle circuit. Therefore reducing leakage power consumption of portable devices such as cell phones and laptop computers is highly desirable for a longer battery lifetime. This paper proposes three different CMOS designs of modulo 4 adders and modulo 4 multipliers with decreased leakage current. Two leakage reduction methods namely transistor stacking and reverse body bias are presented in this work. All the designs are simulated with and without the application of leakage reduction techniques and the readings are tabulated with supply voltages of 1volt and 0.5volt. The simulation results of modulo 4 adders show that for all the three designs the combined effect of (RBB + Stack ) leakage reduction method gives the least leakage current of10.69nA, 6.42nA and 45.65nA respectively at Vdd=1volt. In multipliers, the combined leakage reduction method gives the least leakage current of 21.55nA, 12.17nA and 25.25nA respectively. In modulo 4 adders, the maximum leakage power reduction is observed in design I and in modulo 4 multipliers design II shows maximum % leakage reduction. The circuits have been simulated with HSPICE using MOSFET models of level 54 for 90nm process technology.