• DocumentCode
    3212483
  • Title

    Optimal register allocation in high level synthesis

  • Author

    Aranake, Sandeep ; Raj, Vijay ; Vashi, Mehul ; Youn, Hee Y.

  • Author_Institution
    Texas Univ., Arlington, TX, USA
  • fYear
    1993
  • fDate
    5-6 Mar 1993
  • Firstpage
    71
  • Lastpage
    75
  • Abstract
    A methodology for the register allocation problem in high-level synthesis based on the scanline sweep algorithm is introduced. The algorithm is computationally efficient and easy to understand and to implement, and it guarantees an optimal number of registers for nonpipelined designs. In this method, a set of registers is available from which the best one can be chosen by the allocator for variable binding. The method has proved to be useful in constructive allocation strategies in which the operators and variables are simultaneously considered for binding for interconnect cost optimization. The allocation program is written in C and it is integrated into the DAGAR high-level synthesis system
  • Keywords
    C language; circuit layout CAD; logic CAD; DAGAR; allocation program; constructive allocation strategies; high level synthesis; interconnect cost optimization; nonpipelined designs; optimal register allocation; register allocation problem; scanline sweep algorithm; variable binding; Algorithm design and analysis; Cost function; Design optimization; Flow graphs; High level synthesis; Optimization methods; Pipeline processing; Registers; Throughput; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
  • Conference_Location
    Kalamazoo, MI
  • Print_ISBN
    0-8186-3430-8
  • Type

    conf

  • DOI
    10.1109/GLSV.1993.224477
  • Filename
    224477