DocumentCode
3212539
Title
DPSC SRAM transparent test algorithm
Author
Kim, Hong-Sik ; Kang, Sungho
Author_Institution
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
fYear
2002
fDate
18-20 Nov. 2002
Firstpage
145
Lastpage
150
Abstract
We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the additional steps and additional hardware to generate signatures. This paper describes how to convert a traditional March algorithm to a transparent one. The transformed algorithm is much simpler and the test time can be reduced very much. In addition, it can detect some additional faults that the original algorithm cannot detect.
Keywords
CMOS memory circuits; SRAM chips; built-in self test; integrated circuit design; integrated circuit testing; CMOS SRAM; March algorithms; SRAM dynamic power supply current transparent test algorithms; current measurement; current sensors; fault detection; signature generation; test time reduction; transparent BIST; transparent memory testing; Built-in self-test; Current supplies; Fault detection; Hardware; Heuristic algorithms; Life testing; Power supplies; Random access memory; Read-write memory; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1825-7
Type
conf
DOI
10.1109/ATS.2002.1181702
Filename
1181702
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