Design and implementation of a hybrid SET-CMOS based hi-speed and power efficient pulse divider circuit

Hybrid SET-CMOS circuits which combine the merits of both the SET and CMOS promises to be a practical implementation for future low power ultra-dense VLSI/VLSI circuit design. In this work, an SET-CMOS hybrid pulse divider circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based pulse divider circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.