Crosstalk fault reduction and simulation for clock-delayed domino circuits

In recent years, domino logic has received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic, that realizes any logic gate, has been proposed. Moreover, the domino logic has another drawback in that it is very sensitive to noise induced by crosstalk. Therefore, we focus our attention on crosstalk faults in CD domino circuits. In order to realize an efficient fault simulation, in this paper we propose a new method of target fault reduction, considering conflicts of signal values in the circuit and dominance of faults. In addition, we introduce a faster fault simulation method, which uses only logic values without handling details of the timing events of circuits.