DocumentCode
3212617
Title
Clock partitioning for testability
Author
Einspahr, Kent L. ; Seth, Sharad C. ; Agrawal, VishwaniD
Author_Institution
Concordia Coll., Seward, NE, USA
fYear
1993
fDate
5-6 Mar 1993
Firstpage
42
Lastpage
46
Abstract
An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented
Keywords
clocks; flip-flops; logic testing; sequential circuits; Contest sequential test generator; Podem-based test generator; clock partitioning; complexity; flip-flops; path lengths; sequential circuits; test generation; testability; Benchmark testing; Circuit testing; Clocks; Design for testability; Educational institutions; Feedback; Flip-flops; Partitioning algorithms; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224484
Filename
224484
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