Title :
Epoch IC design system response to VHDL/VITAL requirements
Author :
Hinchliffe, Frederick
Author_Institution :
Cascade Design Autom., Concord, MA, USA
Abstract :
This paper describes the impact that recent changes to VHDL in the area of ASIC modeling will have upon the Epoch IC design system. Epoch delay modeling and simulation support have been implemented to provide for the critically important needs of post-layout simulation
Keywords :
integrated circuit design; ASIC modeling; Epoch IC design system; VHDL; VITAL; delay modeling; post-layout simulation; simulation support; Acceleration; Accuracy; Application specific integrated circuits; Design automation; Design methodology; Electronics industry; Integrated circuit modeling; Libraries; Logic; Timing;
Conference_Titel :
Northcon/94 Conference Record
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-9995-1
DOI :
10.1109/NORTHC.1994.643364
