DocumentCode
3212661
Title
A VLSI-based digital multilayer neural network architecture
Author
Kim, Young-Chul ; Shanblatt, Michael A.
Author_Institution
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
fYear
1993
fDate
5-6 Mar 1993
Firstpage
27
Lastpage
31
Abstract
An architecture and a statistical model for a pulse-mode digital multilayer neural network (DMNN) are presented. The model uses simple logic gates as basic computing units. Modular design techniques lead to an extremely compact and flexible network architecture for VLSI implementation. An example network for character recognition and its performance are presented
Keywords
VLSI; character recognition equipment; feedforward neural nets; logic gates; neural chips; VLSI-based digital multilayer neural network; character recognition; computing units; flexible network architecture; logic gates; pulse mode; statistical model; Artificial neural networks; Character recognition; Computer architecture; Logic gates; Multi-layer neural network; Neural networks; Neurons; Probability; Stochastic processes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-3430-8
Type
conf
DOI
10.1109/GLSV.1993.224487
Filename
224487
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