A new hybrid topology for network on chip

With the advancements in semiconductor chip manufacturing technology, it has been possible to put the various components of a system with more than one hundred processors, on a single chip. Network on chip (NoC) has been used as an effective communication platform for such systems. Due to the delays induced by routers and other equipment employed in NoC, the performance of communications for chips using this architecture is usually less than that of bus based versions. It is expected that a combined solution can provide benefits of both. In this paper, with the goal of reducing delays associated with on-chip communications, five new hybrid topologies have been proposed. Then, a dominant topology has been selected among the candidates and a method for routing, based on dominant topology, has been provided. Simulation results are presented to evaluate the proposed methods.