Modeling stuck-open faults in CMOS iterative circuits

Considers testability criteria for stuck-open faults in one-dimensional, unilateral, iterative circuits of CMOS combinational cells, and gives necessary and sufficient conditions for the testability of such faults. These conditions are extended to include stuck-open C-testability of the circuit. The authors consider the problem of test patterns which may be invalidated by the presence of delays in the input changes and propose restrictions to be imposed during the test vector computation in order to guarantee the robustness of the test pattern