DocumentCode :
3212698
Title :
Modeling stuck-open faults in CMOS iterative circuits
Author :
Macii, Enrico ; Xu, Qing
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fYear :
1993
fDate :
5-6 Mar 1993
Firstpage :
14
Lastpage :
17
Abstract :
Considers testability criteria for stuck-open faults in one-dimensional, unilateral, iterative circuits of CMOS combinational cells, and gives necessary and sufficient conditions for the testability of such faults. These conditions are extended to include stuck-open C-testability of the circuit. The authors consider the problem of test patterns which may be invalidated by the presence of delays in the input changes and propose restrictions to be imposed during the test vector computation in order to guarantee the robustness of the test pattern
Keywords :
CMOS integrated circuits; combinatorial circuits; fault location; logic testing; CMOS iterative circuits; combinational cells; delays; input changes; robustness; stuck-open C-testability; stuck-open faults; test vector computation; testability; testability criteria; Circuit faults; Circuit testing; Logic testing; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-3430-8
Type :
conf
DOI :
10.1109/GLSV.1993.224490
Filename :
224490
Link To Document :
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