A ROMless LFSR reseeding scheme for scan-based BIST

In this paper, we present a new LFSR reseeding scheme for scan-based BIST, suitable for circuits with random-pattern-resistant faults. The proposed scheme eliminates the need of a ROM for storing the seeds since the reseedings are performed dynamically by inverting some selected bits of the LFSR register. A time-to-market efficient algorithm is also presented for selecting the reseeding points in the test sequence, as well as a proper seed at each point. This algorithm targets complete fault coverage and minimization of the resulting test length and hardware overhead. Experimental results on ISCAS ´85 and ISCAS ´89 benchmark circuits demonstrate the advantages of this new LFSR reseeding approach in terms of area overhead and test application time.