Title :
Modeling the vertical constraints in VLSI channel routing
Author :
Jovanovic, Antonije D.
Author_Institution :
Dept. of Electr. Eng., Toledo Univ., OH, USA
Abstract :
Demonstrates that the vertical constraint graph (VCG) is not a complete representation of the vertical constraints of a channel, and proposes an edge-weight augmented VCG that is proved to be complete. Examples demonstrate the feasibility of a deterministic approach to the locally optimal resolution of cyclic vertical constraints when the information provided by the new model is used
Keywords :
VLSI; graph theory; network routing; VLSI channel routing; cyclic vertical constraints; deterministic approach; edge-weight augmented VCG; locally optimal resolution; vertical constraint graph; vertical constraints; Computational geometry; Information geometry; Routing; Very large scale integration; Wire; Wiring;
Conference_Titel :
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-3430-8
DOI :
10.1109/GLSV.1993.224491
