Title :
Diagnosis of Byzantine open-segment faults [scan testing]
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Taiwan
Abstract :
This paper addresses the problem of locating the stuck-open faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty signals, our goal is to further narrow down the faults to a few suspected segments. With such a technique, the silicon inspection time could be dramatically slashed when the fault occurs to a long-running wire with a large number of fanouts. The algorithm is based on our previous inject-and-evaluate paradigm using symbolic simulation. It is fast and accurate. For ISCAS85 benchmark circuits with only one stuck-open fault, the first-hit index is 4.5 on the average within 10 seconds of CPU time.
Keywords :
boundary scan testing; fault diagnosis; fault simulation; flip-flops; inspection; integrated circuit modelling; integrated circuit testing; logic testing; 10 s; Byzantine open-segment fault diagnosis; IC stuck-open faults; Si; computation time; faulty signal identification; first-hit index; large wire fanout; long-running wires; scan flip-flops; scan testing; silicon inspection time; symbolic simulation inject-and-evaluate methods; Circuit faults; Circuit simulation; Fault diagnosis; Flip-flops; Inspection; Pulp manufacturing; Signal processing; Silicon; Testing; Wire;
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
Print_ISBN :
0-7695-1825-7
DOI :
10.1109/ATS.2002.1181719