DocumentCode :
3212912
Title :
An embedded built-in-self-test approach for analog-to-digital converters
Author :
Hsieh, Sheng-Hung ; Hsiao, Ming-Jun ; Chang, Tsin-Yuan
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2002
fDate :
18-20 Nov. 2002
Firstpage :
266
Lastpage :
271
Abstract :
In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (VOSE), gain error (VGE), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 μm 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256μs, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.
Keywords :
CMOS integrated circuits; analogue-digital conversion; built-in self test; integrated circuit testing; 0.35 micron; 256 mus; 8 bit; CMOS IP4M process; analog-to-digital converters; differential nonlinearity error; embedded built-in-self-test approach; gain error; integral nonlinearity error; offset error; sampling rate; testing time; Analog-digital conversion; Artificial intelligence; ISO standards;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1825-7
Type :
conf
DOI :
10.1109/ATS.2002.1181722
Filename :
1181722
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3212912
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