Embedded test solution as a breakthrough in reducing cost of test for system on chips

The cost of test for SoCs (system-on-chips) is tremendous, especially for large and complex designs. Although the high price of ATE (Automatic Test Equipment) is recognized as the primary contributor of test cost, and is therefore most highlighted, high test costs are also caused by factors related to engineering flows ranging from design to manufacturing. In this paper, the discussion will focus on test cost reduction, with all such factors taken into account. A potential difficulty in this discussion is that it is generally difficult to achieve higher quality and lower cost at the same time. In working with several leading edge semiconductor companies in the United States and Japan, the authors have observed and analyzed the whole picture of current flows in design and manufacturing test, including quantitative study of the cost of test. Based upon the results of this analysis, a proposed solution is analyzed, based upon effectiveness in achieving two goals: higher quality and lower costs.